Structured Graph Models: An Tool for VLSI Design Efficient

Hierarchical graph models are a powerful tool for describing VLSI circuits. They combine the representation of a hierarchical decomposition of a circuit with a graph description of its topological structure in terms of components and connections. Structured Graphs are an example of such models. In this paper we consider the graph-theoretic problems of spanning trees and Steiner trees in structured graphs. These have connections with the global routing problems in VLSI circuits. 1 I n t r o d u c t i o n The motivation for defining structured graphs is provided by the increasing complexity of integrated circuits, and the task of developing designs and specifications for them. One way to consider VLSI design problems is to do hierarchical decomposition to reduce the circuit complexity to a manageable size. Our proposed model is the